motorola semiconductor application note order by an1767/d (motorola order number) rev. 0, 09/98 ? motorola, inc., 1998 dragonball? power management dragonball ? power management motorolas dragonball series of integrated processors have been widely adopted for hand-held pda system designs. the power management of these processors is one of the key factors in the success of hand-held products. the MC68328 and mc68ez328 are the currently available dragonball processors, and both contain the same power control module. this application note describes the function of the power control unit in detail. dragonball common reference platform figure 1 shows a common mc68ez328-based pda design. it includes a pen-input touch panel, an lcd panel, a communications port (rs232 or irda), memory, a speaker or buzzer, and a pager receiver. figure 1. mc68ez328-based system example timer module ice module interrupt controller static core 68ec000 rtc spi master lcdc pulse with modulator 8/16-bit bus interface power control i/o ports uart irda bootstrap dramc chip select pll touch panel a/d rf/if flex/pocsag ram/dram rom/flash decoder (mc68177) rs232 transceiver (mc145583) infared transceiver lcd panel audio amp (mc34119) 32.768 khz or 38.4 khz mc68ez328 aa1912
2 dragonball? power management motorola dragonball power modes content organization please refer to the following list for a description of this application notes contents. dragonball common reference platform ......................................................................................... .1 content organization......................................................................................................... ........... 2 dragonball power modes ....................................................................................................... ............ 2 burst mode ................................................................................................................... ................ 3 doze mode .................................................................................................................... ............. 3 sleep mode ................................................................................................................... ................ 4 power consumption test ....................................................................................................... ............. 4 test hardware set-up ......................................................................................................... ......... 4 normal mode test............................................................................................................. ........... 4 burst mode test .............................................................................................................. ............. 5 doze mode test ............................................................................................................... .......... 5 sleep mode test .............................................................................................................. ............. 6 conclusions.................................................................................................................. ....................... 7 dragonball power modes based on application needs, the dragonball can operate in any of four modes: normal mode, burst mode, doze mode, and sleep mode. properly applied, power-saving techniques can result in minimal power consumption for the entire system and can thus extend battery life. the current consumption values specified in the dragonball users manual represent the maximum normal mode value as well as a sleep mode value. in real-world applications, doze mode is used most of the time the system is up and running. the dragonball processors acheive power savings by minimizing bus activity while optimizing system and cpu clock frequencies. figure 2 shows the clock tree model of the internal phase lock loop (pll) and power management circuit. d figure 2. clock tree model of internal pll please refer to the following list for a description of the elements of figure 2. ? external clock inputboth 32.768khz and 38.4khz crystals can be used as the pll input frequency. a frequency of 32.768khz is recommended. throughout this application note, 32.768khz, or simply 32khz, will be assumed as the input reference. ? voltage-controlled oscillator (vco)this is the output frequency of the plls vco. its default output frequency, for a 32khz input, is 16.58mhz. the vco frequency can be changed from approximately 9mhz to 23 mhz through programming of the p and q values of frequency select sysclk divider cpu clock burst control pixclk divider sysclk vco peripheral modules pixel clock cpu clock external clock input aa1913
dragonball power modes motorola 3 frequency select register. note that the vco frequency can be maintained at its default value while achieving power saving requirements for the system. ? sysclkthis clock signal is derived from the vco through a divider. by default the MC68328 divides by 1, generating a sysclk frequency of 16.58mhz after reset. by default the mc68ez328 divides by 2 (ez328 has a 1-bit prescaler which is set by default), so sysclk is normal mode ? 8.29mhz after reset. the sysclk output is applied to all dragonball peripheral modules except the rtc, which is clocked directly from the external 32khz crystal. ? pixel clockthis clock is used for the lcd pixel generation. it is separated from sysclk so that changing the system-clock frequency for power saving will not affect the lcd screen refresh rate. ? cpu clockthis clock signal is input to the cpu core. since the cpu consumes a major portion of overall power, changing the cpu clock frequency and burst duty cycle will directly affect the dragonball power consumption. in normal mode the system is running at its highest frequency, and the dragonball consumes maximum power. the maximum system clock frequency for both the MC68328 and mc68ez328 is 16.58mhz. the 68k core performance at this frequency is 2.7 million instructions per second (mips). if the system requires a peak performance lower than 2.7 mips, a lower system clock frequency can be used by programming the system-clock divider accordingly. the system-clock frequency can be rescaled from 16mhz down to 1mhz for the MC68328 by programming the system-clock divider bits in the pll control register ($fff200). for the mc68ez328, the system-clock frequency can be scaled down to 512khz by programming the prescaler and divider bits. because most of the modules, such as the uart, spi, timer, and pwm, use the system clock for bit rate generation, changing the system-clock frequency will also change the system timing. therefore, once a system-clock frequency is selected, it should not be changed during system operation. burst and doze modes are then used for power saving. burst mode if the user wants to keep the modules enabled at a high system-clock frequency during normal operation without requiring maximum cpu performance, burst cpu clock-control mode can be enabled. the period of a burst is 1 ms, and the duty-cycle of a burst is controlled by the value of the width bits in the power control register. the user can choose from 1/31 to 31/31 of 1 ms of cpu active time for every 1 ms burst period. a width value of zero will place the cpu in doze mode. smaller values of width will reduce system power consumption. burst mode is often used in data-polling applications. burst mode is entered by setting the pc en bit and program the width bits of the power control register. burst mode is disabled automatically when there is an interrupt event. clearing the pc en bit will also disable burst control. doze mode for many pda applications, the system takes only a little time to process tasks the user requests, after which the system waits again for user commands, such as a touch screen input. during the waiting period, some peripherals like the lcd screen must be active. therefore, the developer can stop the cpu in these waiting periods using doze mode. as mentioned before, doze mode is entered by setting the pc en bit and clearing the width bits of the power control register. doze mode is disabled automatically when there is an interrupt event.
4 dragonball? power management motorola power consumption test sleep mode in sleep mode the cpu and all peripherals but the rtc are in an inactive state. sleep mode is entered by disabling pll, thus stopping the system clock. only the external 32khz clock still inputs to the rtc module. because 32khz is a low-frequency signal, the rtc consumes less than 1 ua. when disabling the pll to enter sleep mode, please follow the pll shut-down sequence specified in the dragonball users manual. sleep mode is disabled automatically when there is an interrupt event. note that upon wake-up it takes 1 ms for the pll to stabilize and provide a system clock power consumption test both the MC68328 and mc68ez328 users manuals state that the maximum current consumption at 3.3v is 20 ma for normal mode and 20ua for sleep mode. the user should remember that system up does not always mean full running. burst or doze mode can be used. in burst/doze mode, current consumption is substantially less than 20ma. power tests with the MC68328 and mc68ez328 show that they both consume similar amounts of current in the same configuration. refer to the following sections for benchmark data. test hardware set-up figure 3 shows the hardware set-up for this power measurement. figure 3. hardware configuration for power consumption test normal mode test figure 4 graphs the following test condition: the cpu is continuously running; the lcd controller is enabled and initialized to 240x160 b/w; the rtc is enabled; and the rom chip-select is configured for 1 wait state. 68ez328 8-bit rom aa1914 power supply v cc a v
power consumption test motorola 5 figure 4. normal mode test burst mode test figure 5 diagrams the following test condition: a burst-duty cycle value of 1/31 clock is applied to the cpu clock; the lcd is enabled and is initialized to 240x160 b/w; the rtc is enabled; and the rom chip select is configured for 1 wait state. figure 5. burst mode test doze mode test refer to figure 6 for a diagram of the following test condition: the cpu clock is stopped (0/31 burst-duty cycle); the lcd is enabled and is initialized to 240x160 b/w; the rtc is enabled; and the rom chip select is configured for 1 wait state. aa1915 sysclk = 16 mhz 15 sysclk = 4 mhz sysclk = 1 mhz 20 10 5 3.0 3.3 3.6 current, ma voltage, v aa1916 sysclk = 16 mhz 15 sysclk = 4 mhz sysclk = 1 mhz 20 10 5 3.0 3.3 3.6 current, ma voltage, v
6 dragonball? power management motorola power consumption test figure 6. doze mode test sleep mode test figure 7 graphs the following test condition: the pll is turned off and only the rtc is enabled. figure 7. sleep mode test aa1917 sysclk = 16 mhz 15 sysclk = 1 mhz 20 10 5 3.0 3.3 3.6 current, ma voltage, v aa1918 15 20 10 5 3.0 3.3 3.6 current, m a voltage, v
conclusions motorola 7 conclusions the most effective power-control strategy is to run the cpu at its highest system speed until no cpu cycles are needed and then to enter doze mode. other power-saving system-design techniques include the use of interrupts, instead of data polling, and configuring unused i/o pins to be inputs. it is important not to enable internal pull-up resisters unless it is necessary. (internal pull-up resisters are 100k ohms.) finally, the user should disable external devices before entering sleep mode. use of the modes and techniques listed in this application note should result in an optimally low system power dissipation for the dragonball processors.
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